1. Field of the Invention
The present general inventive concept relates to image processing systems, and more particularly, to an image forming apparatus to enhance a degree of integration and efficiency of a hyper print video controller (HPVC) during generation of video data from input data.
2. Description of the Related Art
Generally, an image forming apparatus prints video data in 1-, 2-, 4-, and 8-laser beam mode according to each set. However, due to a certain mechanical or electric effect, the laser beam of the image forming apparatus starts to print video data in a dot position different from the set position.
The conventional image forming apparatus compensates for this problem with a sub-module, serving as a buffer, installed in a hyper print video controller (HPVC). The video data generated in the HPVC is processed through a buffer in the HPVC to compensate for the dots, the buffer being in a range from a minimum “0” to a maximum “128,” generated by a difference between laser beams.
When video data is printed as print material, dots between laser beams are printed in different positions, due to a mechanical or electromagnetic effect, etc. Since video data is printed synchronously with a video clock (VCLK), a buffer compensating for dots is generally configured to include 128 flip-flops. Although this different position printing phenomenon appears generally in 5 dots, the buffer is designed to compensate for 128 dots. Therefore, in order to compensate for two dots, the buffer is set such that video data can pass two flip-flops.
However, the conventional image forming apparatus requires as many as 128 flip-flops to compensate for dots, and this causes a great number of gate counts during a chip lay out. When a number of gate counts is increased, a size of a chip included in the buffer must also be increased; energy consumption therefore increases; and the degree of integration and the efficiency of the chip are reduced.